Improving the Performance of the IDEA Cryptographic Algorithm Using FPGAs

Nowadays, the cryptography field is on the increase in the telecommunications world, because of this there is a constant need of more secure and efficient cryptographic algorithms. Thus, a lot of research is being done in order to try to improve the current algorithm performance. At present, one of the alternatives under research is the implementation of these algorithms in FPGAs (Field-Programmable Gate Arrays), which offer excellent features. In this work, we present a detailed research of the IDEA cryptographic algorithm implementation in Virtex FPGAs. Nine different hardware implementations are presented, which are compared with each other and with the algorithm software implementation. In addition, the conclusions of this detailed research and the possible future work lines are shown. In short, the implementation of the IDEA algorithm using FPGAs offers advantages over software implementation thanks to the use of the intrinsic parallelism (pipelining and replication), resulting in a performance that surpasses in 16 times the software version. Key-Words: Computer Security and Cryptography, IDEA Cryptographic Algorithm, FPGA (FieldProgrammable Gate Array), Performance, Experience using Handel-C